Solving Satisfiability Problems Using Logic Synthesis and
Takayuki Suyama, Makoto Yokoo, Hiroshi Sawada
Proceedings of the 31st Hawaii International
Conference on System Sciences (HICSS-31),
This paper presents new results on an innovative approach for
solving satisfiability problems (SAT), i.e.,
creating a logic circuit that is specialized to solve
each problem instance on Field Programmable Gate Arrays (FPGAs).
This approach becomes feasible
due to the recent advances in FPGA technologies and
automatic logic synthesis technologies.
We have developed an algorithm which is suitable for implementing on a logic
circuit. This algorithm is equivalent to the Davis-Putnam
procedure with a powerful dynamic variable ordering heuristic.
The algorithm does not have a large memory structure like a stack;
thus sequential accesses to the memory do not become a bottleneck in
Simulation results show that this method can solve
a hard random 3-SAT problem with 400 variables within 20
minutes at a clock rate of 1MHz.